Fine tuning a sampling clock of analog signals having digital information for optimal digital display

ABSTRACT

Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device ( 92 ). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system ( 96 ) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism ( 48 ), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit ( 94 ).

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates to signal processing used in field ofelectronics, and more particularly, to a method and system for finetuning a sampling clock of analog signals having digital information foroptimal digital display. The method and system are based on fine tuningfrequency and phase of a sampling clock of the analog signals, forsampling incoming analog signals having digital information within anoptimal sampling period, thereby enabling optimal display by a digitaldisplay device.

Currently, most common methods and systems of transmitting computerdisplay information to display devices are based on using analogtransmission. For example, the VGA format was originally defined by VESA(Video Electronics Standards Association) and other organizations forthe purpose of providing a universal format for transmitting analogsignals carrying digital pixel information, from a transmitter, such asa PC (personal computer) graphics card, to an analog display device, asdescribed in “Monitor Timing Specifications, VESA and Industry Standardsand Guidelines for Computer Display Monitor Timing, Version 1.0,Revision 0.8, Adoption Date: Sep. 17, 1998”, Milpitas, Calif., USA.

FIG. 1 is a block diagram illustrating such an exemplary VGA interfaceof a transmitter 10 in a typical computer, used in the transmission ofanalog signals having digital pixel information to a receiver of adisplay device 12. Image information stored in a frame buffer istransmitted to the receiver of display device 12, by converting digitalpixel information stored in the frame buffer to analog pixel informationtransmitted to the receiver of display device 12 using a digital toanalog converter (DAC). In current VGA formats, analog pixel informationis transmitted from transmitter 10 to the receiver of display device 12along three high speed analog transmission lines, marked R (red), G(green) and B (blue), which are the three basic color components of animage.

In addition to analog pixel information, digital synchronizationinformation, known in the art by the terms ‘vertical sync’ and‘horizontal sync’, and indicated in FIG. 1 by the terms ‘Vsync’ and‘Hsync’, is sent out to mark the beginning of each frame, and thebeginning of each display line, respectively. Vsync and Hsync are sentalong two separate lines (as shown in FIG. 1), composite to a singleline, or embedded within the green color component of the analog signal.A transmitter timing clock, referred to in FIG. 1 as ‘Tx clock’,provides a timing signal featuring a frequency or rate at which digitalpixel information is transmitted from transmitter 10 to the receiver ofdisplay device 12 by an analog signal. Digital pixel informationtransmitted along the R, G, and B, analog transmission lines, and thedigital synchronization information signals, Hsync and Vsync, are allsynchronized to the transmitter timing clock (Tx clock).

Several standard organizations, such as VESA, have defined manydifferent types of display formats and/or standards. Each display formator standard provides the number of active (displayed) pixels and active(displayed) lines, as well as polarity of Vsync and Hsync, pulse width,cycle time, and position of the active displayed information relative toVsync and Hsync synchronization pulses. Each display format also definesthe frequency or rate of the above described transmitter timing clock(Tx clock), as the frequency or rate at which the digital pixel valuesare read from the frame buffer, converted to analog signal by the threeDACs, and subsequently forwarded to the receiver of the display device.The VGA display interface format was originally defined for analogdisplays, where each one of the three electronic beam guns within thedisplay device is controlled by the associated analog signal forwardedby the VGA interface.

There is currently a transition from using analog display devices tousing digital display devices. Due to the existence of extensive andwidespread electronic infrastructure, ordinarily, digital displaydevices are designed and manufactured for operating with the abovedescribed digital to analog VGA interface, but their pixel elements needto be fully defined and individually addressed within the digitaldisplay device. For example, in an LCD (liquid crystal display) monitoreach pixel is an active element controlling light transmission. In aplasma display monitor each pixel element is a light generator. Theluminance information for each color component of each pixel isextracted from the same digital to analog VGA interface, by way ofanalog to digital conversion, such as by using an analog to digitalconverter device. This extraction method is a very challenging taskbecause it requires automatic detection of the transmission format andreconstruction of the transmitter timing clock (Tx clock), at thedigital display device from the incoming analog RGB signals, and theHsync and Vsync digital synchronization information signal pulses.

FIG. 2 is a close-up view of an exemplary transmitted analog signal 15having digital information of a single pixel as part of a transmissionformat of an analog signal, illustrating pixel timing parameters at areceiver of a digital display device. It is well known that duringreception of the analog signals featuring pixels having an R, G, or B,component, at a receiver, such as a receiver of a digital displaydevice, the time period of each pixel is composed of a transition timeperiod 20 during which signal level transition occurs, and a stable timeperiod 22 during which pixel sampling occurs. The signal receiver of thedigital display device needs to generate, known in the art asreconstruct, parameters of a sampling clock, using a phase locked loop(PLL) mechanism (functioning with hardware and/or software components)locked to the leading edge of Hsync, or, depending upon the particulartype of display format or standard, locked to the trailing edge ofHsync. Frequency of the sampling clock usually exhibits an extent ordegree of instability, known as ‘jitter’, shown in FIG. 2 asreconstructed clock phase locked loop (PLL) jitter time periods 28 and29, which causes the optimal sampling time period 24 to be shorter thanthe stable time period 22. Sampling analog signals during thereconstructed clock phase locked loop (PLL) jitter time periods 28 and29, results in less than optimal analog to digital conversion, andsubsequently, results in less than optimal display by the digitaldisplay device.

There is thus a need for, and it would be highly advantageous to have amethod and system for fine tuning a sampling clock of analog signalshaving digital information for optimal digital display. Moreover, thereis a need for such an invention which is readily commercially applicableto essentially any type of electronic system where transmitted analogsignals are destined for display by a digital display device.

SUMMARY OF THE INVENTION

The present invention relates to a method and system for fine tuning asampling clock of analog signals having digital information for optimaldigital display. The method and system are based on fine tuningfrequency and phase of a sampling clock of the analog signals, forsampling incoming analog signals having digital information within anoptimal sampling period, thereby enabling optimal display by a digitaldisplay device.

Thus, according to the present invention, there is provided a method forfine tuning a sampling clock of analog signals having digitalinformation for optimal digital display, comprising the steps of: (a)receiving digital synchronization signals of the analog signals anddetecting format based on the received digital synchronization signals;(b) setting an initial frequency value of the sampling clock by settinga phase locked loop division factor value equal to a digital horizontalsynchronization signal cycle based on the detected format, and setting aphase value of the sampling clock at a phase locked loop mechanism; (c),fine tuning the initial frequency value of the sampling clock by finetuning the phase locked loop division factor value, and fine tuning thephase value of the sampling clock, for synchronizing the phase lockedloop mechanism with an optimal sampling period; (d) sampling thereceived analog signals having digital information within an optimalsampling period; and (e) receiving and displaying the digital imagepixel information by a digital display device.

According to further features in preferred embodiments of the method ofthe invention described below, the digital synchronization signals arevertical sync and horizontal sync.

According to further features in preferred embodiments of the method ofthe invention described below, detecting the format is performed byknowing the format a priori.

According to further features in preferred embodiments of the method ofthe invention described below, detecting the format is performed bymeasuring values of various parameters of the vertical sync and thehorizontal sync signals, and comparing the measured parameter values tocorresponding parameter values of known transmission formats stored in adatabase.

According to further features in preferred embodiments of the method ofthe invention described below, the phase locked loop mechanism used forgenerating the sampling clock is selected from the group consisting of(i) a phase locked loop hardware mechanism, featuring operation of aplurality of hardware components and elements, (ii) a phase locked loopsoftware mechanism, featuring operation or execution of a plurality ofsoftware computer programs of software instructions or protocols using asuitable computer operating system, and, (iii) an operative combinationof (i) and (ii).

According to further features in preferred embodiments of the method ofthe invention described below, the optimal sampling period is at centerof a stable pixel time, given by deducting from a pixel cycle time apixel transition time and twice a phase jitter of the sampling clock.

According to further features in preferred embodiments of the method ofthe invention described below, the fine tuning of the phase value of thesampling clock is realized using a phase delay of the horizontal sync atthe phase locked loop mechanism.

According to further features in preferred embodiments of the method ofthe invention described below, step (c) comprises the step of: (i)searching for and identifying transitional pixels within an input imageof the analog signals, and determining a phase value at which a pixelbreak point occurs for each transitional pixel.

According to further features in preferred embodiments of the method ofthe invention described below, the break point of each transitionalpixel defines a singular point within the pixel, having a phase valuewhere value of the pixel starts to change from a stable region ofpreceding pixel in same horizontal line to a transitional region of thepixel.

According to further features in preferred embodiments of the method ofthe invention described below, the break point phase value of the pixelvalue is measured while the phase value is swept to get a curve of thepixel value as a function of the phase value.

According to further features in preferred embodiments of the method ofthe invention described below, step (c) further comprises the step of:(ii) searching for and identifying a phase value of a break point foreach identified transitional pixel of the input image, by sweeping thephase values of the analog signals.

According to further features in preferred embodiments of the method ofthe invention described below, step (c) further comprises the step of:(iii) determining an error value of the phase locked loop divisionfactor value, the error value being a difference between an actual phaselocked loop division factor value and a phase locked loop divisionfactor value matching the initial frequency value of the sampling clockto a frequency value of a transmitter timing clock.

According to further features in preferred embodiments of the method ofthe invention described below, if there is no unique solution to anerror value of the phase locked loop division factor value, there issearching for and identifying additional transitional pixels.

According to further features in preferred embodiments of the method ofthe invention described below, whereby step (iii) comprises the step of:(1) checking if the error value of the phase locked loop division factorvalue equals zero, whereby if the phase locked loop division factorvalue equals zero, there is determining a corrected value of the phasevalue of the sampling clock.

According to further features in preferred embodiments of the method ofthe invention described below, whereby step (iii) further comprises thestep of: (2) searching for and identifying the error value of the phaselocked loop division factor value by searching through an entire rangeof allowed error values.

According to further features in preferred embodiments of the method ofthe invention described below, whereby step (iii) further comprises thestep of: (3) checking uniqueness of a phase locked loop division factorvalue.

According to further features in preferred embodiments of the method ofthe invention described below, whereby step (c) further comprises thestep of: (iv) fine tuning the phase value of the sampling clock, if theerror value of the phase locked loop division factor value equals zero,and if the error value of the phase locked loop division factor value isnot equal to zero, there is fine tuning the phase locked loop phasevalue based on values of position and phase of the identifiedtransitional pixels.

According to another aspect of the system of the present invention,there is provided a system for fine tuning a sampling clock of analogsignals having digital information for optimal digital display,comprising: (a) a receiver for receiving digital synchronization signalsof the analog signals and detecting format based on the received digitalsynchronization signals; (b) a control unit for setting and fine tuninga phase locked loop division factor value and setting a phase value ofthe sampling clock; (c) a phase locked loop mechanism for generating asampling signal controlled by the control unit; (d) at least one analogto digital conversion device for sampling the received analog signalshaving digital information within an optimal sampling period; and (e) adigital display device for receiving and displaying the digital imagepixel information by a digital display device.

According to further features in preferred embodiments of the system ofthe invention described below, the digital synchronization signals arevertical sync and horizontal sync.

According to further features in preferred embodiments of the system ofthe invention described below, detecting the format is performed byknowing the format a priori.

According to further features in preferred embodiments of the system ofthe invention described below, detecting the format is performed bymeasuring values of various parameters of the vertical sync and thehorizontal sync signals, and comparing the measured parameter values tocorresponding parameter values of known transmission formats stored in adatabase.

According to further features in preferred embodiments of the system ofthe invention described below, the phase locked loop mechanism used forgenerating the sampling clock is selected from the group consisting of(i) a phase locked loop hardware mechanism, featuring operation of aplurality of hardware components and elements, (ii) a phase locked loopsoftware mechanism, featuring operation or execution of a plurality ofsoftware computer programs of software instructions or protocols using asuitable computer operating system, and, (iii) an operative combinationof (i) and (ii).

According to further features in preferred embodiments of the system ofthe invention described below, the optimal sampling period is at centerof a stable pixel time, given by deducting from a pixel cycle time apixel transition time and twice a phase jitter of the sampling clock.

According to further features in preferred embodiments of the system ofthe invention described below, the fine tuning of the phase value of thesampling clock is realized using a phase delay of the horizontal sync atthe phase locked loop mechanism.

Implementation of the method and system for fine tuning a sampling clockof analog signals having digital information for optimal digital displayof the present invention involves performing or completing selectedtasks or steps manually, semi-automatically, fully automatically, and/ora combination thereof. Moreover, according to actual instrumentationand/or equipment used for implementing a particular preferred embodimentof the disclosed method and system, several selected steps of thepresent invention could be performed by hardware, by software on anyoperating system of any firmware, or a combination thereof. Inparticular, as hardware, selected steps of the invention could beperformed by a computerized network, a computer, a computer chip, anelectronic circuit, hard-wired circuitry, or a combination thereof,involving a plurality of digital and/or analog, electrical and/orelectronic, components, operations, and protocols. Additionally, oralternatively, as software, selected steps of the invention could beperformed by a data processor, such as a computing platform, executing aplurality of computer program types of software instructions orprotocols using any suitable computer operating system.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is herein described, by way of example only, withreference to the accompanying drawings. With specific reference now tothe drawings in detail, it is stressed that the particulars shown are byway of example and for purposes of illustrative description of thepreferred embodiments of the present invention only, and are presentedin the cause of providing what is believed to be the most useful andreadily understood description of the principles and conceptual aspectsof the present invention. In this regard, no attempt is made to showstructural details of the present invention in more detail than isnecessary for a fundamental understanding of the invention, thedescription taken with the drawings making apparent to those skilled inthe art how the several forms of the invention may be embodied inpractice. In the drawings:

FIG. 1 is a block diagram illustrating an exemplary VGA interface of atransmitter in a typical computer, used in the transmission of analogsignals having digital pixel information to a receiver of a displaydevice;

FIG. 2 is a close-up view of an exemplary transmitted analog signalhaving digital information of a single pixel as part of a transmissionformat of an analog signal, illustrating pixel timing parameters at areceiver of a digital display device;

FIG. 3 is a schematic diagram illustrating an exemplary transmittedanalog signal of a single display line, and parameters thereof, as afunction of time, according to the transmission format partlyillustrated in FIG. 2;

FIG. 4 is a block diagram illustrating an exemplary preferred embodimentof a phase locked loop (PLL) mechanism (functioning with hardware and/orsoftware components), used for generating a sampling clock (Rx clock)locked to received Hsync, in accordance with the present invention;

FIG. 5 is a schematic diagram illustrating an exemplary preferredembodiment of sampling a transitional pixel as a function of phase, inaccordance with the present invention; and

FIG. 6 is a block diagram illustrating an exemplary preferred embodimentof the system for fine tuning a sampling clock of analog signals havingdigital information for optimal digital display, in accordance with thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention relates to a method and system for fine tuning asampling clock of analog signals having digital information for optimaldigital display. The method and system are based on fine tuningfrequency and phase of a sampling clock of the analog signals, forsampling incoming analog signals having digital information within anoptimal sampling period, thereby enabling optimal display by a digitaldisplay device.

A main aspect of novelty and inventiveness of the method and system ofthe present invention is whereby a relatively small amount ofinformation from input signals is required for rapidly and accuratelydetermining values of the frequency and phase of a sampling clock. Morespecifically, after measuring and obtaining pixel values while sweepingthe phase values of signals using a phase locked loop (PLL) mechanism(functioning with hardware and/or software components), the method andsystem of the present invention determine values of two parameters, (i)error of an initial frequency value of the sampling clock, herein, alsoreferred to as ‘Rx clock’, being proportional to error value of aninitial phase locked loop (PLL) division factor value, and (ii) phase ofthe sampling clock (Rx clock), without need for making additionalmeasurements based on values of these two parameters.

The method and system of the present invention for fine tuning asampling clock of analog signals having digital information, in general,and having standard video image information, in particular, for optimaldigital display, are independent of the type of analog signaltransmitter, as long as there is proper identification of the analogtransmission format. Furthermore, implementing the present inventionmaintains high image quality by not requiring use of a low-pass filteron input signals.

Based upon the above indicated aspects of novelty, inventiveness, andadvantages, the present invention successfully overcomes shortcomings,and widens the scope, of presently known methods and systems ofprocessing analog signals having digital information for digitaldisplay, for example, which are based on maximizing pixel differences orminimizing signal noise. Moreover, the method and system of the presentinvention are commercially applicable to essentially any type ofelectronic setup where transmitted analog signals are destined fordisplay by a digital display device.

It is to be understood that the present invention is not limited in itsapplication to the details of the order or sequence of steps ofoperation or implementation of the method, or to the details of type,composition, construction, arrangement, and order, of the components andelements of the system, set forth in the following description andaccompanying drawings. The present invention is capable of otherembodiments or of being practiced or carried out in various ways.Although steps and components similar or equivalent to those describedherein can be used for practicing or testing the present invention,suitable steps and components are described herein.

It is also to be understood that unless otherwise defined, all technicaland scientific words, terms, and/or phrases, used herein have the samemeaning as commonly understood by one of ordinary skill in the art towhich this invention belongs. Phraseology, terminology, and, notation,employed herein are for the purpose of description and should not beregarded as limiting. For example, the following description refers tothe use of a phase locked loop (PLL) mechanism (functioning withhardware and/or software components), in order to illustrateimplementation of the present invention. It is to be fully understood,as is well known in the art of signal processing, that the phase lockedloop (PLL) mechanism refers to (i) a phase locked loop (PLL) ‘hardware’mechanism, featuring operation of a plurality of hardware components andelements, or (ii) a phase locked loop (PLL) ‘software’ mechanism,featuring operation or execution of a plurality of software computerprograms of software instructions, algorithms, or protocols, using asuitable computer operating system, or (iii) an operative combination of(i) and (ii).

Steps, components, operation, and implementation of a method and systemfor fine tuning a sampling clock of analog signals having digitalinformation for optimal digital display, according to the presentinvention, are better understood with reference to the followingdescription and accompanying drawings. Throughout the followingdescription and accompanying drawings, like reference numbers refer tolike components or elements.

In the following description of the method and system of the presentinvention, included are main or principal steps and sub-steps, and mainor principal devices, mechanisms, components, and elements, needed forsufficiently understanding proper ‘enabling’ utilization andimplementation of the disclosed method and system. Accordingly,description of various possible required and/or optional preliminary,intermediate, minor, steps, sub-steps, devices, mechanisms, components,and/or elements, which are readily known by one of ordinary skill in theart, and/or which are available in the prior art and technicalliterature relating to signal processing, are at most only brieflyindicated herein. For example, with reference to FIG. 1, the followingdescription of the method and system of the present invention focuses onthat part of signal processing performed between the VGA connector and a‘digital’ type of display device 12, even though signal processing alsotakes place before and after these components.

In Step (a) of implementing the method and system for fine tuning asampling clock of analog signals having digital information for optimaldigital display, there is receiving digital synchronization signals ofthe analog signals and detecting the format based on the receiveddigital synchronization signals.

Again referring to FIG. 1, a block diagram illustrating an exemplary VGAinterface of a transmitter 10 in a typical computer, used in thetransmission of analog signals having digital pixel information to areceiver of a display device 12, where, hereinafter, for describing themethod and system of the present invention, display device 12 is a‘digital’ type of display device, and is referred to as digital displaydevice 12. Image information stored in a frame buffer is transmitted tothe receiver of digital display device 12, by converting digital pixelinformation stored in the frame buffer to analog pixel informationtransmitted to the receiver of digital display device 12 using a digitalto analog converter (DAC). In current VGA formats, analog pixelinformation is transmitted from transmitter 10 to the receiver ofdigital display device 12 along three high speed analog transmissionlines, marked R (red), G (green) and B (blue), which are the three basiccolor components of an image.

In addition to analog pixel information, digital synchronizationsignals, known in the art by the terms ‘vertical sync’ and ‘horizontalsync’, and indicated in FIG. 1 by the terms ‘Vsync’ and ‘Hsync’, is sentout to mark the beginning of each frame, and the beginning of eachdisplay line, respectively. Vsync and Hsync are sent along two separatelines (as shown in FIG. 1), composite to a single line, or embeddedwithin the green color component of the analog signal. A transmittertiming clock, referred to in FIG. 1 as ‘Tx clock’, provides a timingsignal featuring a frequency or rate at which digital pixel informationis transmitted from transmitter 10 to the receiver of digital displaydevice 12 by an analog signal. Digital pixel information transmittedalong the R, G, and B, analog transmission lines, and the digitalsynchronization information signals, Hsync and Vsync, are allsynchronized to the transmitter timing clock (Tx clock).

Detecting the format based on the received digital synchronizationsignals, Vsync and Hsync, is performed by either knowing the format apriori, or by measuring values of various parameters of the Vsync andHsync signal pulses, and comparing these measured parameter values tocorresponding parameter values of known transmission formats stored in adatabase, for example, involving use of look-up-tables, as is known inthe art.

FIG. 3 is a schematic diagram illustrating an exemplary transmittedanalog signal 34. and parameters thereof, as a function of time,according to the transmission format partly illustrated in previouslydescribed FIG. 2, a close-up view of an exemplary transmitted analogsignal 15 having digital information of a single pixel as part of atransmission format of an analog signal, illustrating pixel timingparameters at a receiver of a digital display device. With reference toFIG. 3, the VESA monitor timing specifications standard defines severalparameters of transmitted analog signals as follows:

-   Hsync 30: digital horizontal synchronization signal.-   Vsync (not shown in FIG. 3): digital vertical synchronization    signal.-   Tx clock frequency 32: frequency of the transmitter timing clock (Tx    clock), also referred to as transmitted pixel clock frequency, in    terms of number of pixels per unit time.-   Hsync pulse width 36: in terms of number of pixels, and polarity    thereof.-   Vsync pulse width (not shown in FIG. 3): in terms of number of    lines, and polarity thereof.-   Horizontal back porch 38: number of blank pixels from end of Hsync    pulse to first active pixel.-   Vertical back porch (not shown in FIG. 3): number of blank lines    from end of Vsync pulse to first active line.-   Active pixels in a line 40: also referred to as pixel resolution.-   Active lines in a frame (not shown in FIG. 3): also referred to as    line resolution.-   Hsync cycle 42: representing total number of horizontal pixels in a    single Hsync cycle. This parameter is used for setting an initial    value of a phase locked loop (PLL) division factor of the analog    signal sampling clock (Rx clock), as described in detail in Step    (b).-   Vsync cycle (not shown in FIG. 3): representing total number of    lines in a single Vsync cycle, or in a single frame.-   Refresh rate: Vsync frequency=pixel clock frequency/(Hsync cycle X    Vsync cycle).

Typically, measured values of a sub-set of the above list of parametersof transmitted digital synchronization signals, Vsync and Hsync, areused for detecting the format of the received image of the analogsignals having digital pixel information. For example, pulse width,pulse cycle, and pulse polarity, of each of the Hsync and Vsync signals,whereby pulse polarity is determined according to whether the particulardigital synchronization signal is sent with active high or active low.

In Step (b), there is setting an initial frequency value of the samplingclock (Rx clock) by setting a phase locked loop (PLL) division factorvalue equal to Hsync cycle based on the detected format, and setting aphase value of the sampling clock (Rx clock), at a phase locked loop(PLL) mechanism.

Information and data obtained in Step (a) for detecting the format ofthe transmitted analog signals are used for performing Step (b), wherebyfrequency of the sampling clock (Rx clock) is estimated. It is to beunderstood that although the transmitter ‘knows’ the frequency of thetransmitter clock (Tx clock), this frequency is usually not transmitted.Initial phase value is set to an arbitrary value.

The sampling clock (Rx clock) is generated using a phase locked loop(PLL) mechanism, whereby the initial frequency value of the samplingclock (Rx clock) is set equal to the frequency value of Hsync multipliedby Hsync cycle (which is equal to the phase locked loop (PLL) divisionfactor value). FIG. 4 is a block diagram illustrating an exemplarypreferred embodiment of a phase locked loop (PLL) mechanism (functioningwith hardware and/or software components), generally indicated by thedashed line enclosure and referred to as phase locked loop (PLL)mechanism 48. Phase locked loop (PLL) mechanism 48, used for generatingsampling clock (Rx clock) 60, is selected from the group consisting of(i) a phase locked loop (PLL) ‘hardware’ mechanism, featuring operationof a plurality of hardware components and elements, (ii) a phase lockedloop (PLL) ‘software’ mechanism, featuring operation or execution of aplurality of software computer programs of software instructions orprotocols using a suitable computer operating system, and, (iii) anoperative combination of (i) and (ii).

As shown in FIG. 4, Hsync 30 is operatively input to phase detector 54following a phase delay 50. Phase detector 54 compares input signals 68and 66. Output signal of phase detector 54 is proportional to the phasedifference between input signals 68 and 66. Loop filter 56 is a low passfilter, filtering the output signal of phase detector 54 and providing aclear and stable DC voltage level to a voltage controlled oscillator(VCO) 58. Voltage controlled oscillator (VCO) 58 generates samplingclock (Rx clock) 60. Initial frequency value of sampling clock (Rxclock) 60 generated by phase locked loop (PLL) mechanism 48 equals Hsyncfrequency value multiplied by an initial phase locked loop (PLL)division factor value 64.

Sampling clock (Rx clock) 60 is divided by initial phase locked loop(PLL) division factor value 64 by a clock divider 62. Output signal 66of clock divider 62, corresponding to an estimated number of totalhorizontal pixels in a single Hsync cycle, is sent to a feedback inputof phase detector 54. Phase locked loop (PLL) division factor value 64is initially set with the value of Hsync cycle 42 (FIG. 3) obtained fromdefinition of the transmitted format of the received digitalsynchronization signals, which was detected according to previouslydescribed Step (a).

In Step (c), there is fine tuning the frequency value of the samplingclock (Rx clock), by fine tuning the phase locked loop (PLL) divisionfactor value, and fine tuning the phase value of the sampling clock (Rxclock), for synchronizing the phase locked loop (PLL) mechanism with anoptimal sampling period.

As previously described in preceding Step (b), the Hsync frequency valueand the initial phase locked loop (PLL) division factor value are usedfor setting the initial frequency value of the sampling clock (Rxclock). The initial phase locked loop (PLL) division factor value shouldbe equal to Hsync cycle determined in Step (a) for proper pixelsampling. Fine tuning, by correcting, the initial phase locked loop(PLL) division factor value is sometimes required when the graphics cardat the transmitter is not producing exact Hsync cycle as expected by thedisplay device at the receiver. For example, if standard value of Hsynccycle is not exactly kept at the PC display card, fine tuning isrequired to find the actual value of Hsync cycle, and load it to thephase locked loop (PLL) mechanism as a division factor value.

If the initial phase locked loop (PLL) division factor value is notmaking the frequency of the sampling clock matching the frequency clockat the transmitter (that is, frequency of the transmitter timing clock(Tx clock) is not exactly equal to frequency of the sampling clock (Rxclock), the sampling point within each pixel will vary along the displayhorizontal line. As a result, it will be impossible to sample all pixelsat their optimum sampling point (24 in FIG. 2), and therefore, finetuning of the initial phase locked loop (PLL) division factor value isrequired.

Referring to FIG. 5, a schematic diagram illustrating an exemplarypreferred embodiment of sampling a transitional pixel as a function ofphase, when pixels are sampled at the pixel transition time 20 (FIG. 2),instability in pixel sampling value is noticed due to phase locked loop(PLL) jitter. In most cases, transition noise 72 is a result of thephase locked loop (PLL) jitter. The sampling clock (Rx clock) frequencyinstability is seen as noise, and the displayed image is seen withvertical bars of noise stripes. The number of noise stripes is equal tothe error of the initial phase locked loop (PLL) division factor value.The error value of the initial phase locked loop (PLL) division factorvalue is the difference between the estimated value of Hsync cycle atthe receiver and the value of Hsync cycle at the transmitter.

After adjusting phase locked loop (PLL) division factor value,fine-tuning of the phase is required to guarantee sampling of the analogincoming RGB signals at the optimum sampling period 24. As stated above,there is synchronizing the phase locked loop (PLL) mechanism with anoptimal sampling period. The optimal sampling period, is at the centerof the stable pixel time, given by deducting from pixel cycle time thepixel transition time and twice the phase jitter of Rx clock. The reasonfor deducting twice the phase jitter is that the diversion can be to theright or to the left. In the preferred embodiment of the presentinvention, fine tuning of the phase value of the sampling clock(indicated as Rx clock phase 52 in FIG. 4) is realized using Hsync phasedelay 50 at the phase locked loop (PLL) mechanism 48 as seen in FIG. 4.Increasing the phase delay is delaying Hsync signal, result in delayingthe sampling point (or moving the sampling point to the right).

The phase delay (noted as Rx clock phase 52 at FIG. 4) is measured indegrees, where 0° means no delay, and 360° means one Rx clock cycledelay. In many phase locked loop (PLL) mechanisms or devices, the phaseresolution is more than 1° (for example: in 32 step resolution,(360/32)=11.25° each step), however, for clarity reasons and withoutlimiting the scope of the present invention, a 1° resolution phase unitis used throughout this description.

The following description of sub-steps (i)-(iv) of Step (c) includesdetailed description of the preferred embodiment of the just describedfine tuning of phase locked loop (PLL) division factor value and finetuning of phase locked loop (PLL) Rx clock phase. Before startdescribing those steps, few formal definitions of the problem are to bedefined, few observations that are used in the synthesis and analysis ofthe method and system disclosed in the preferred embodiment of thepresent invention are to be discussed, and a common location inside thepixel time called ‘Break point’ is to be defined for all of the‘Transitional pixels’.

The following definitions are used for defining the following steps moreformally and clearly:

‘Hsync_cycle’ as defined hereinafter is the estimated number of Rx clockcycles within one horizontal line. This estimation is based on step (a)disclosed above. Rx clock is sometimes shortly written as “clock”hereinafter. The Hsync_cycle is used for the phase locked loop (PLL)division factor value.

‘Real_Hsync_cycle’ as defined hereinafter is the number of Tx clockcycles within one horizontal line. The goal of the fine tuning procedureis tuning Hsync_cycle to be equal to Real_Hsync_cycle.

‘Delta_HC’ as defined hereinafter is equal toHsync_cycle−Real_Hsync_cycle, and is referred to as ‘error value of theinitial phase locked loop (PLL) division factor value’. Delta_HC can bepositive or negative, for Hsync_cycle greater than or less thanReal_Hsync_cycle, respectively.

‘Maximum_Delta_HC’ as defined hereinafter is an assumption on themaximum value of absolute delta_HC, used in the described method andsystem.

‘Phase delay setup’ as defined hereinafter is equal to Rx clock phase 52in degrees and is sometimes shortly written as ‘phase’ hereinafter. Thephase delay is accomplished by delaying Hsync at the phase locked loop(PLL) input. Phase increase from 0° to 360° results in moving thesampling point one clock cycle to the right on the time axis. 0°corresponds to no delay and 360° corresponds to one Rx clock delay.

‘Coordinate system (x,y)’ as defined hereinafter, contains twoparameters. ‘x’ defines horizontal pixel position in Rx clock. x=0 atHsync leading edge. ‘y’ defines vertical pixel position in lines. y=0 atfirst line after Vsync rising edge (or falling edge, as decided by thepreferred embodiment).

‘P(x,y)’ as defined hereinafter, is the pixel measured value at position(x,y). The value can be the pixel luminance value or pixel colorcomponent intensity value. The color component can be any selected one,with preference to the Green color component.

‘Transitional pixel’ as defined hereinafter, is a pixel that thedifference between its value and its predecessor pixel value is greaterthan a predefined threshold.

P(x,y) is a transitional pixel if:[P(x,y)−P(x−1,y)]>threshold

When the characteristic (pixel value) of rising edge is equal to thecharacteristic of the falling edge, both positive and negativetransitions can be used for defining a transitional pixel. In that case,P(x,y) is a transitional pixel if:ABS[P(x,y)−P(x−1,y)]>thresholdwhere ‘ABS’ is an abbreviation of‘Absolute value of . . . ’

After defining the aforementioned definitions, main objects of thepresent invention are formulated as follows:

Frequency fine tuning: finding Delta_HC, so Hsync_cycle value can becorrected to be equal to Real_Hsync_cycle value.

Phase fine-tuning: correcting the Phase of the sampling clock at thereceiver such that the sampling of all pixels be done at the optimalsampling period of the pixels, as defined in FIG. 2.

The following observations are used in the synthesis and analysis of thepreferred embodiment of the method and system for fine tuning a samplingclock of analog signals having digital information for optimal digitaldisplay:

When Delta_HC is not equal to zero, vertical noise stripes are noticedat transitional pixels. The number of vertical noise stripes is equal toABS(Delta_HC), and the vertical noise stripes are evenly separated alongthe display total width. The total width includes active and blankingintervals and therefore there may be cases where not all the verticalnoise stripes are noticed on the displayed image due to the fact thatsome of the vertical noise stripes may be located in the blank area. Thehorizontal distance between two adjacent vertical noise stripes (inpixels, or in clocks) is equal to:stripe_distance=Hsync_cycle/ABS (Delta_(—) HC)Noise stripes are noticed only in transitional pixels. Wherever theimage is constant, the stripes are not noticed.

When Delta_HC equal to zero, the image is seen correctly when all pixelsare sampled at their optimal sampling period, or is seen as a very noisyimage when the sampling points are located in the pixel transition time,assuming image is not completely constant.

When Delta_HC is not equal to zero, and noise stripes are noticed,changing phase delay results in all stripes moving in horizontaldirection, keeping stripe distance unchanged.

If Delta_HC>0, while increasing the phase delay stripes are moving tothe right (or positive) direction. If Delta_HC<0, while increasing thephase delay stripes are moving to the left (or negative) direction.

The Phase delay 50 has a cycle of 360°. The meaning is that whenDelta_HC is not equal to zero, and noise stripes are noticed, increasingphase delay from phase 0° to phase 360° results in stripes moving‘stripe distance’ in horizontal direction. Stripe distance is defined in(1) above, in clocks (or pixels).

As part of the present invention, an exemplary preferred embodiment foracquiring specific location inside the pixel time is described hereinbelow, where that specific location featuring, for all of the‘transitional pixels’ defined above, a common location inside the pixeltime. This common location, for all of the transitional pixels insidethe pixel time, always appears at the same location in relation to thestarting point of the pixel and is noted hereinafter as ‘singularpoint’. The pixel break point (defined hereinafter) may be used assingular point.

The preferred embodiment of the method and system for fine tuning asampling clock of analog signals having digital information for optimaldigital display features identifying transitional pixels within an inputimage, and for each transitional pixel determining the phase value atwhich pixel break point occurs. Transitional pixel identification isdone with a constant phase, noted as ‘PHi’. PHi phase can be arbitrarychosen, as long as it is fixed alone the acquisition phase.

Referring to FIG. 5, The Pixel Time 78 is the cycle time of one pixel.Inside the cycle time we may define transitional pixel 70 including abreak point 74. The break point itself may be a singular point too. Thefollowing description is only an example for acquiring singular points.It is possible to choose other criterions for singular points thatperform the same tasks.

The break point 74 of each transitional pixel 70 P(x,y) is defining thesingular point within the pixel. As stated before, there may be othersingular points within the pixel that can be used for the same purpose.The following description, using break point as the singular point, doesnot limit the scope of the solution.

The break point of pixel P(x,y) is defined hereinafter as a phase value80 where the pixel value start to change from the stable region of thepreceding pixel in the same horizontal line, P(x−1,y), to thetransitional region of pixel P(x,y), as seen in FIG. 5. In other words,the break point is defined as the phase value at the beginning of thetransitional pixel P(x,y). From hereinafter, any reference to a breakpoint is equivalent to a singular point.

The ‘Phase error value’ (or ‘PH_Error’) is defined as the maximumabsolute measured error value of the phase at the singular point. Thephase error value is a function of the measurement system and the phaselocked loop (PLL) jitter.

To find the break point phase 80, the pixel value P(x,y) is measuredwhile the phase value is swept to get the curve of pixel value as afunction of phase value. The phase sweep should make sure the breakpoint phase is included in the sweep. It is noted that sampling ofP(x,y) at phase 0° is the same as sampling P(x−1,y) at phase 360°.

FIG. 5 shows by the vertical bars 72 that repetitive sampling during thepixel transition noise time 72 results in different values for P(x,y).The sampling clock jitter and uncertainty during the sample and holdtime in the ADC (analog to digital converter) usually cause thetransition noise 72. A low pass filter (for example, an FIR filter) isapplied on the sampling points for producing a smooth curve.

The break point phase value is searched for on the smooth curve. Thedifference between the true phase value of the break point and themeasured phase value of the break point found from the smooth curve isequal to the break point phase error value.

The following sub-steps (i)-(iv) of Step (c) feature detaileddescription of the preferred embodiment for fine tuning the phase lockedloop (PLL) division factor value and fine tuning the phase locked loop(PLL) Rx clock phase.

In sub-step (i) of Step (c), there is searching for and identifyingtransitional pixels within an input image of the analog signals.

Set phase value equal to an arbitrary phase value (PHi), and search forT+1 transitional pixels within the input image (transitional pixel wasdefined previously).

Mark the transitional pixels as follows: Pi(xi,yi), i=0, 1, 2, . . . , T

Order the transitional pixels according to their horizontal position:xi>xi−1 for i=1, 2, . . . T. The minimum horizontal difference betweentwo adjacent transitional pixels, Pi(xi,yi) and Pj(xj,yj) where j=i−1,should be greater than (PH_Error/360°) multiplied byMinimum_Stripe_width, where Minimum_Stripe_Width is defined asHsync_cycle/Maximum_Delta_HC, (PH_Error was defined previously).Transitional pixels that do not fulfill this requirement are removedfrom the list.

As the number of transitional pixels T+1 is increased, the probabilityto find unique Delta_HC is increased too. If there is no unique solutionto Delta_HC in sub-step (2) of sub-step (iii), there is searching forand identifying additional transitional pixels.

It is explained in sub-step (3) of sub-step (iii), that it is alsopossible to find out if a given set of transitional pixels is capable ofproviding a unique solution to Delta_HC, or there is a need to addadditional transitional pixels.

In sub-step (ii) of Step (c), there is searching for and identifying aphase value of a break point for each identified transitional pixel ofthe input image, by sweeping phase values of the analog signals.

For each transitional pixel find the singular point phase value. Withoutloosing generality, the singular point is defined here as the breakpoint, although other points within the transitional pixel may be used.One way of finding transitional pixel break point phase value is byperforming a phase sweep on phase delay 50, that includes the breakpoint, measure the pixel value at each phase value, perform low passfiltering (for example FIR filter) on the measured values in order toobtain a smooth curve, and find the phase value where the break pointoccurs.

The break point phase of transitional pixel Pi(x,y) is markedhereinafter with PHi. The maximum absolute phase error value is markedhereinafter as PH_Error.

In sub-step (iii) of Step (c), there is determining an error value ofthe initial phase locked loop (PLL) division factor value.

The purpose of this step is to find the error value of the initial phaselocked loop (PLL) division factor value, which was defined as thedifference between the actual phase locked loop (PLL) initial divisionfactor value (Hsync_Cycle) and the phase locked loop (PLL) divisionfactor value that matches the Rx clock frequency to the transmittertiming clock (Tx clock) frequency value (defined previously asReal_Hsync_Cycle).

Horizontal difference and phase difference for each pair of transitionalpixels (Pi, Pj), where i=1, 2, . . . T, and j<i , are defined asfollows:

-   1) dxij is the horizontal difference between Pi(xi, yi) and Pj(xj,    yj),    dxij=xi−xj, i=1, 2, . . . T, and j=0, . . . , i−1-    dxij is always a positive number because in sub-step (i) of    Step (c) the transitional pixels were organized in incremental order    (If i>j than xi>xj).-   2) dPHij is the phase difference between Pi(xi, yi) and Pj(xj, yj)    modulo 360°, dPHij=(PHi−PHj) modulo 360°.-   Modulo 360° operator guarantee that the result (noted here as dPHij)    is in the range of 0° to 359°. This is done by adding N×360° if the    result is outside the range, where N is the integer number that    brings dPHij to the required range.

ABS(Phase) is defined hereinafter as an operator that return the phasedistance relative to 0° or 360°, whichever is closer.ABS(Phase)=Phase WHEN Phase≦180°, ELSE 360°−Phase

In sub-step (1) of sub-step (iii), there is checking if the error valueof the initial phase locked loop (PLL) division factor value equalszero.

If for each pair of transitional pixels (Pi, Pj) as defined above, thevalue of ABS(dPHij) is less than or equal to 2×PH_Error, then there isno error of the initial phase locked loop (PLL) division factor value,and Delta_HC=0. The value of ABS(dPHij) is compared to twice PH_Error isbecause PHi and PHj measured error values may be of opposite signs.

If the error value of the initial phase locked loop (PLL) divisionfactor value equals 0, jump to sub-step (iv) of step (c)—determining acorrected value of the phase of the sampling clock, Rx clock, of thedigital synchronization signals. Otherwise, continue to the nextsub-step.

In sub-step (2) of sub-step (iii), there is searching for andidentifying the error value of the initial phase locked loop (PLL)division factor value.

The error value of the initial phase locked loop (PLL) division factorvalue, Delta_HC, is found by a search procedure through the entire rangeof allowed Delta_HC, from −Maximun_Delta_HC to +Maximum_Delta_HC. Thesearch procedure is terminating correctly if it finds the Delta_HC,which is the correct error value of the initial phase locked loop (PLL)division factor value, and this value is unique (no multiple Delta_HCs).

The following values are defined for sub-step (2) of sub-step (iii)search procedure:

-   The search index for the absolute value of the error value of the    initial phase locked loop (PLL) division factor value is marked by    dHC.-   The horizontal distance in Rx clock cycles between two adjacent    vertical noise stripes is marked as Stripe_distance and is defined    as:    Stripe_distance=Hsync_cycle/dHC-    For each pair of transitional pixels (Pi,Pj) with horizontal    difference dxij and phase difference dPHij, dxij_corrected is    defined as:    dxij_corrected=dxij modulo stripe_distance-    where the modulo function guarantee that the result is in the range    of 0 to stripe_distance−1. The modulo operation is done by    subtracting N×stripe_distance from dxij, where N is a natural number    (0, 1, 2, . . . ) that brings the result to the required range.

This step for finding Delta_HC (error value of the initial phase lockedloop (PLL) division factor value) is based on the fact that at thecorrect positive Delta_HC for all pairs of transitional pixels (Pi, Pj),the ratio of dx_(ij—)corrected to Stripe_width is equal to the ratio ofdPH_(ij) to 360°, and at the correct negative Delta_HC for all pairs oftransitional pixels (Pi, Pj), the ratio of dx_(ij) _(—) corrected toStripe_width is equal to one minus the ratio of dPH_(ij) to 360°. Thecomparison should take into account the phase measured error value fordPH_(ij), which is 2×PH_Error. In formal writing:

FOR each dHC in the range of 1 to Maximum_Delta_HC do the following [1]and [2]:

-   [1] If for all pairs of transitional pixels (Pi,Pj) as defined above    the following relation holds:    ABS {[360°×(dx _(ij) _(—) corrected/Stripe_distance)−dPH _(ij)]    modulo 360°}≦2×PH_Error Than Delta_(—) HC=+dHC-   [2] If for all pairs of transitional pixels (Pi,Pj) as defined above    the following relation holds:    ABS {[360°×(dx _(ij) _(—) corrected/Stripe_distance)+dPH _(ij)]    modulo 360°}≦2×PH_Error Than Delta_(—) HC=−dHC-    End the FOR loop.    Notice that ABS(phase) is used as defined at the beginning of    sub-step (iii) of Step (c).

If there is no case that fulfill [1] or [2], Delta_HC may be greaterthan Maximum_Delta_HC, or there is a measurement error, or the inputimage was not stable during sub-steps (i) or (ii) of step (c). It mightalso be the result of incorrect format detection that leads to acompletely wrong phase locked loop (PLL) initial setting. For example,format detection of input resolution was 640×480, unfortunately theactual input was 720×480—both formats have the same Hsync and Vsynctiming characteristics but different initial phase locked loop (PLL)division factor value.

At this point correct phase locked loop (PLL) division factor value bysetting it to:

Set phase locked loop (PLL) division factor value=Hsync_cycle−Delta_HC,and go to sub-step (iv) of Step (c) to determine the phase value.

If there is more than one case that fulfills [1] or [2], (if the resultof the search process is not unique) then the result of the searchprocess is not unique, and there is adding additional transitionalpixels according to sub-step (i) of step (c), finding break point phasevalues of the additional pixels according to sub-step (ii) of step (c),and then repeating sub-step (2) of sub-step (iii).

To avoid these non-unique cases enter the following sub-step.

In sub-step (3) of sub-step (iii), there is checking uniqueness of theinitial phase locked loop (PLL) division factor value.

To avoid the cases that the result of the previous sub-step searchprocess is not unique, selection of transitional pixels found insub-step (i) of step (c) of the algorithm should be checked.−Mark dHC=ABS (Delta_(—) HC)The following two conditions, B1 and B2, check if two transitionalpixels can distinguish between two error values of the initial phaselocked loop (PLL) division factor values Delta_HC(1) and Delta_HC(2):

-   B1) A pair of transitional pixels Pi(xi , yi) and Pj(xj, yj), with    horizontal difference dxij=xi−xj (assuming xi>xj) can distinguish    between +dHC(1) and +dHC(2) and also between −dHC(1) and −dHC(2) if    the ratio of dxij_corrected to stripe_width is not the same for    dHC(1) and dHC(2). In formal writing:    ABS{[dx _(ij) _(—) corrected(1)/stripe_distance(1)]−[dx _(ij) _(—)    corrected(2)/stripe_distance(2)]}<2×PH_Error/360°  [8]-   B2) A pair of transitional pixels Pi(x_(i), y_(i)) and Pj(x_(j),    yj), with horizontal difference dx_(ij)=x_(i)−x_(j) (assuming    x_(i)>x_(j)) can distinguish between +dHC(1) and −dHC(2) and also    between −dHC(1) and +dHC(2) if the sum of both ratio of    dx_(ij—)corrected to stripe_width is not equal to 1. In formal    writing:    ABS{[dx _(ij) _(—) corrected(1)/stripe_distance(1)]+[dx _(ij) _(—)    corrected(2)/stripe_distance(2)]−1}<2×PH_Error/360°  [9]

In equations [8] and [9], the break point phase error value (PH_Error)is taken into account. Twice that value is required because the errorvalues for Pi and Pj may be of different signs.

Sub-step summary: for avoiding multiple matches when dHC=ABS(Delta_HC)is in the range of 1 to Maximum_Delta_HC, every pair of dHC(1) anddHC(2), in the range of 1 to Maximum_Delta_HC should be checked thatthere is at least one pair of transitional pixels that equation [8]holds, and at least one pair of transitional pixels that equation [9]holds.

In sub-step (iv) of Step (c), there is fine tuning the phase value ofthe sampling clock (Rx clock).

This step assumes that the error value of the initial phase locked loop(PLL) division factor value was fine tuned, or corrected, in sub-step(iii) of Step (c) such that the receiver sampling clock (Rx clock)frequency is exactly the same as the transmitter clock (Tx clock)frequency. The purpose of this step is to adjust Rx clock phase to therequired value for sampling by the ADC the incoming pixels at theoptimal sampling period. IF Delta_HC is equal to zero, there iscontinuing with sub-step (1) of sub-step (iv). If Delta_HC is not equalsto zero, there is continuing with sub-step (2) of sub-step (iv).

In sub-step (1) of sub-step (iv), there is fine tuning the phase valueof the sampling clock (Rx clock), when the error value of the phaselocked loop (PLL) division factor value equals zero.

All transitional pixels break point measured phase (marked PHi) havetheoretically the same values, with absolute phase difference of zerobetween each pair of transitional pixels. However, due to measured errorvalue (PH_Error), the maximum absolute phase difference dPHij as wasdefined in sub-step (iii) of Step (c) is limited to 2×PH_Error.

The average value for break point phase is defined as Average (PHi). Thephase margin that bring the sampling point to the center of the optimalsampling period (See FIG. 2) has to be subtracted from Average (PHi).Phase margin is about half of the optimal sampling period.

Therefore, if Delta_HC=0, the phase should be set to:Set Phase={[Average (PHi)]−Phase_Margin} Modulo 360°, i=0, 1, 2, . . . ,T  [3]

Definition of Average (PHi): The phase value is a circular unit, meaningthat phase value of 0° and phase value of 360° refer to sampled pixelslocated at the same relative position. This fact should be taken intoaccount when calculating the Average (PHi) of several phases (and it isalso true for other group operators like Min, Max or Median).

For example:

Average (40°, 50°, 60°)=50°,

Average (350°, 10°, 20°)=(350+370+380)/3=367°=7°.

Instead of Average (PHi) filter operator, another type of filter may beused, for example, a median filter. The median filter arranges the inputphase values in incremental order, and selects as an output the value ofthe center positioned value. For example: Median (355°, 0°, 30°)=0°

Phase_Margin: The phase to subtract from the break point phase for finalphase locked loop (PLL) phase setting. Subtracting this value from thebreak point phase value places the ADC sampling point at the center ofpixel optimal sampling period as shown in FIG. 2.

The Phase margin is found from the transitional time 20 (FIG. 2) of atransitional pixel using the following formula:Phase_Margin=0.5×360°×(1−(transition time/pixel time))

Jump to Step (d).

In sub-step (2) of sub-step (iv), there is fine tuning the phase lockedloop (PLL) phase value, based on values of position (x_(i)) and phase(PHi) of the transitional pixels identified in sub-step (i) of Step (c),when the error value of the initial phase locked loop (PLL) divisionfactor value is not equal to zero.

The division factor value Delta_HC may be corrected without performingthis sub-step, followed by repeating sub-steps (i) to (iv) of Step (c).In this case, this sub-step is not required, because after the finetuning, Delta_HC=0 and sub-step (1) of sub-step (iv) is used forcorrecting the phase. However, repeating sub-steps (i) to (iv) requiresmore processing time, because new measurements are needed for performingsteps (i) and (ii), and a main aspect f the present invention is tosearch for and identify the phase value without needing to repeatmeasurements.

The definitions from sub-step (iii) of Step (c) are herein redefined fortransitional pixels Pi instead of transitional pixel pairs (Pi,Pj) asfollows:

-   Stripe_distance is defined as the horizontal distance in Rx clock    cycles between two adjacent vertical noise stripes.    Stripe_distance=Hsync_cycle/ABS(Delta_HC)-   For each transitional pixels Pi, i=0 to T, xi_corrected is defined    as follows:    x _(i) _(—) corrected=x _(i) modulo stripe_distance-    where the modulo function guarantee the result is in the range of 0    to stripe_distance−1.

Some observations are needed for this sub-step: as was written before,vertical noise stripes occur during sampling at the pixel transition.Moving the vertical stripe left or right can be done by changing thephase, which is the delay on the horizontal sync to the phase lockedloop (PLL). Moving a stripe at the amount of one stripe distancerequires a delay of exactly one Rx clock cycle, which is equal to 360°.Whenever Delta_HC is positive, increasing the phase value moves thestripes to the right. Whenever Delta_HC is negative, increasing thephase value moves the stripes to the left.

Changing phase locked loop (PLL) division factor value changes thenumber of stripes, but at all division factor values, the clock phase atthe beginning of the line will remain unchanged because the phase lockedloop (PLL) is locked at horizontal sync leading edge. Therefore the ideabehind phase delay adjustment is to adjust correct phase at thebeginning of the line, and this phase is going to be also the correctphase after correcting the error value of the initial phase locked loop(PLL) division factor value.

The phase delay is adjusted by moving the break point position to thebeginning of the line by changing the phase value, and than subtractingPhase_Margin value to position the sampling point at the center of theoptimal sampling period as showed in FIG. 2.

For each transitional pixel Pi, the algorithm determine the requiredphase value correction for moving the break point to the beginning ofthe line as follows:

-   If Delta_HC is positive, the phase value correction is done by    subtracting (modulo 360°) from PHi the value of:    360°*(x _(i) _(—) corrected/stripe_distance)=[360°*(x    _(i)/stripe_distance)] modulo 360°-   If Delta_HC is negative, the phase value correction is done by    adding (modulo 360°) to PHi the value of:    360°*(x _(i) _(—) corrected/stripe_distance)=[360°*(x    _(i)/stripe_distance)] modulo 360°

The phase value correction should theoretically be the same value foreach transitional pixel. However, due to error in PHi measure of±PH_Error, the absolute phase difference between minimum and maximumcorrection is 2×PH_Error. An average or median function (as definedabove) should be used to determining the final break point phase valuecorrection.

As noted before, the final phase delay is set as follows:

-   Set Phase=(final break point phase correction—Phase_Margin) modulo    360°-   The Phase delay setting formally written:-   For each Transitional pixel Pi, in range 0 to T do:-   IF Delta_HC>0THEN    Phase(i)=[PHi−360°*(x _(i)/stripe_distance)−Phase_Margin] modulo    360°  [4]-    IF Delta_HC<0 THEN    Phase(i)=[PHi+360°*(x _(i)/stripe_distance)−Phase_Margin] modulo    360°  [5]-    End of IF condition.    Set Phase=Average{Phase(i)}, i=0 to T  [6]

It is understood that other averaging function can be used instead ofAverage function. For example: median function. Both functions aredefined in sub-step (1) of sub-step (iv).

In Step (d), there is sampling the received analog signals havingdigital information within the optimal sampling period.

Referring to FIG. 4, for correcting the initial sampling clock frequencyerror value, proportional to the error value of the initial phase lockedloop (PLL) division factor value, the division factor error valuedetermined in sub-step (iii) of step (c) above as Delta_HC is subtractedfrom the initial division factor value, Hsync_Cycle, and is feed intothe Clock Divider 62 as the Division Factor 64. The corrected value ofthe phase of the sampling clock (Rx clock) of the digitalsynchronization signals, determined above as Set Phase in sub-step (iv)of step (c), is feed into the Phase Delay 50 as the Rx clock phase 52.

After feeding the phase locked loop (PLL) with the correct frequency andphase, the analog to digital converter (ADC) is sampling the incominganalog signals having digital information within the optimal samplingperiod 24 (FIG. 2). In a preferred embodiment of the present invention,the sampled digital information contains digital image pixelsinformation. The digital image pixels information is transmitted to adigital display device for displaying the image.

In Step (e), there is receiving and displaying the digital image pixelinformation by a digital display device.

The received digital image pixels information were sampled at theoptimal sampling period 24 (FIG. 2) and therefore the digital displaydevice should be able to display the received digital image pixelsinformation optimally.

FIG. 6 is a block diagram illustrating an exemplary preferred embodimentof the system, generally referred to as system 90, for fine tuning asampling clock of analog signals having digital information for optimaldigital display, in accordance with the above described method of Step(a) through (e). In FIG. 6, measurement system 96 is used forimplementing previously described Step (a), of receiving digitalsynchronization signals of the analog signals and detecting the formatbased on the received digital synchronization signals. Control unit 94is used for implementing previously described Step (b) of is setting aninitial frequency value of the sampling clock (Rx clock) by setting aphase locked loop (PLL) division factor value equal to Hsync cycle basedon the detected format, and setting a phase value of the sampling clock(Rx clock), at a phase locked loop (PLL) mechanism, and implementingpreviously described Step (c) of fine tuning the frequency value of thesampling clock (Rx clock), by fine tuning the phase locked loop (PLL)division factor value, and fine tuning the phase value of the samplingclock (Rx clock), for synchronizing the phase locked loop (PLL)mechanism with an optimal sampling period. Digital display device 92 isused for implementing previously described Step (e). PLL 48 correspondsto phase locked loop (PLL) mechanism 48 illustrated in previouslydescribed FIG. 4. The analog signals are sampled during the optimalsampling period by the ADC devices shown in system 90 of FIG. 6.

It is appreciated that certain features of the invention, which are, forclarity, described in the context of separate embodiments, may also beprovided in combination in a single embodiment. Conversely, variousfeatures of the invention, which are, for brevity, described in thecontext of a single embodiment, may also be provided separately or inany suitable subcombination.

All publications, patents and patent applications mentioned in thisspecification are herein incorporated in their entirety by referenceinto the specification, to the same extent as if each individualpublication, patent or patent application was specifically andindividually indicated to be incorporated herein by reference. Inaddition, citation or identification of any reference in thisapplication shall not be construed as an admission that such referenceis available as prior art to the present invention.

While the invention has been described in conjunction with specificembodiments and examples thereof, it is evident that many alternatives,modifications and variations will be apparent to those skilled in theart. Accordingly, it is intended to embrace all such alternatives,modifications and variations that fall within the spirit and broad scopeof the appended claims.

1. A method for fine tuning a sampling clock of analog signals havingdigital information for optimal digital display, comprising the stepsof: (a) receiving digital synchronization signals of the analog signalsand detecting format based on said received digital synchronizationsignals; (b) setting an initial frequency value of the sampling clock bysetting a phase locked loop division factor value equal to a digitalhorizontal synchronization signal cycle based on said detected format,and setting a phase value of the sampling clock at a phase locked loopmechanism; (c) fine tuning said initial frequency value of the samplingclock by fine tuning said phase locked loop division factor value, andfine tuning said phase value of the sampling clock, for synchronizingsaid phase locked loop mechanism with an optimal sampling period; (d)sampling said received analog signals having digital information withinan optimal sampling period; and (e) receiving and displaying saiddigital image pixel information by a digital display device.
 2. Themethod of claim 1, whereby said digital synchronization signals arevertical sync and horizontal sync.
 3. The method of claim 1, wherebysaid detecting said format is performed by knowing said format a priori.4. The method of claim 2, whereby said detecting said format isperformed by measuring values of various parameters of said verticalsync and said horizontal sync signals, and comparing said measuredparameter values to corresponding parameter values of known transmissionformats stored in a database.
 5. The method of claim 1, whereby saidphase locked loop mechanism used for generating the sampling clock isselected from the group consisting of (i) a phase locked loop hardwaremechanism, featuring operation of a plurality of hardware components andelements, (ii) a phase locked loop software mechanism, featuringoperation or execution of a plurality of software computer programs ofsoftware instructions or protocols using a suitable computer operatingsystem, and, (iii) an operative combination of (i) and (ii).
 6. Themethod of claim 1, whereby said optimal sampling period is at center ofa stable pixel time, given by deducting from a pixel cycle time a pixeltransition time and twice a phase jitter of the sampling clock.
 7. Themethod of claim 2, whereby said fine tuning of said phase value of thesampling clock is realized using a phase delay of said horizontal syncat said phase locked loop mechanism.
 8. The method of claim 1, wherebystep (c) comprises the step of: (i) searching for and identifyingtransitional pixels within an input image of the analog signals, anddetermining a phase value at which a pixel break point occurs for eachsaid transitional pixel.
 9. The method of claim 8, whereby said breakpoint of each said transitional pixel defines a singular point withinsaid pixel, having a phase value where value of said pixel starts tochange from a stable region of preceding pixel in same horizontal lineto a transitional region of said pixel.
 10. The method of claim 9,whereby said break point phase value of said pixel value is measuredwhile said phase value is swept to get a curve of said pixel value as afunction of said phase value.
 11. The method of claim 10, whereby step(c) further comprises the step of: (ii) searching for and identifying asaid phase value of a said break point for each said identifiedtransitional pixel of the input image, by sweeping said phase values ofthe analog signals.
 12. The method of claim 11, whereby step (c) furthercomprises the step of: (iii) determining an error value of said phaselocked loop division factor value, said error value being a differencebetween an actual said phase locked loop division factor value and asaid phase locked loop division factor value matching said initialfrequency value of the sampling clock to a frequency value of atransmitter timing clock.
 13. The method of claim 12, whereby if thereis no unique solution to a said error value of said phase locked loopdivision factor value, there is searching for and identifying additionalsaid transitional pixels.
 14. The method of claim 12, whereby step (iii)comprises the step of: (1) checking if said error value of said phaselocked loop division factor value equals zero, whereby if said phaselocked loop division factor value equals zero, there is determining acorrected value of said phase value of the sampling clock.
 15. Themethod of claim 14, whereby step (iii) further comprises the step of:(2) searching for and identifying said error value of said phase lockedloop division factor value by searching through an entire range ofallowed said error values.
 16. The method of claim 15, whereby step(iii) further comprises the step of: (3) checking uniqueness of a saidphase locked loop division factor value.
 17. The method of claim 16,whereby step (c) further comprises the step of: (iv) fine tuning saidphase value of the sampling clock, if said error value of said phaselocked loop division factor value equals zero, and if said error valueof said phase locked loop division factor value is not equal to zero,there is fine tuning said phase locked loop phase value based on valuesof position and phase of said identified transitional pixels.
 18. Asystem for fine tuning a sampling clock of analog signals having digitalinformation for optimal digital display, comprising: (a) a receiver forreceiving digital synchronization signals of the analog signals anddetecting format based on said received digital synchronization signals;(b) a control unit for setting and fine tuning a phase locked loopdivision factor value and setting a phase value of the sampling clock;(c) a phase locked loop mechanism for generating a sampling signalcontrolled by said control unit; (d) at least one analog to digitalconversion device for sampling said received analog signals havingdigital information within an optimal sampling period; and (e) a digitaldisplay device for receiving and displaying said digital image pixelinformation by a digital display device.
 19. The system of claim 18,whereby said digital synchronization signals are vertical sync andhorizontal sync.
 20. The system of claim 18, whereby said detecting saidformat is performed by knowing said format a priori.
 21. The system ofclaim 18, whereby said detecting said format is performed by measuringvalues of various parameters of said vertical sync and said horizontalsync signals, and comparing said measured parameter values tocorresponding parameter values of known transmission formats stored in adatabase.
 22. The system of claim 18, whereby said phase locked loopmechanism used for generating the sampling clock is selected from thegroup consisting of (i) a phase locked loop hardware mechanism,featuring operation of a plurality of hardware components and elements,(ii) a phase locked loop software mechanism, featuring operation orexecution of a plurality of software computer programs of softwareinstructions or protocols using a suitable computer operating system,and, (iii) an operative combination of (i) and (ii).
 23. The system ofclaim 1, whereby said optimal sampling period is at center of a stablepixel time, given by deducting from a pixel cycle time a pixeltransition time and twice a phase jitter of the sampling clock.
 24. Thesystem of claim 19, whereby said fine tuning of said phase value of thesampling clock is realized using a phase delay of said horizontal syncat said phase locked loop mechanism.